ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

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United States of America Patent

APP PUB NO 20240322953A1
SERIAL NO

18423519

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An operation unit 2 sets a Flit length according to the number of lanes, a mask pattern length and a mask pattern period for masking a portion corresponding to an SKP OS, and a threshold value for Flit error determination. In an error detector 4, a symbol mask generation unit 25 generates a mask pattern, an error detection unit 28 detects and counts an error in the portion corresponding to Flit by dividing the mask pattern at intervals of a Flit length of a PAM4 signal from a device under test, and masking a portion corresponding to the SKP OS with the mask pattern, and a Flit error detection unit 29 detects and counts an FEC symbol error in the portion corresponding to Flit for each ECC group, and determines the ECC group in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.

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Patent Owner(s)

Patent OwnerAddress
ANRITSU CORPORATIONKANAGAWA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
KIDOKORO, Hisao Kanagawa, JP 6 6

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