MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAME
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United States of America Patent
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Oct 3, 2024
app pub date -
Jun 10, 2024
filing date -
Oct 7, 2019
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Abstract
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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