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Abstract

A computing device comprising input device terminals (x0-x4) for receiving respective analog input signals of the device; output device terminals (p0-p7) for receiving respective analog output signals of the device; rows of analog cells (C00-C01), wherein an analog cell (C00) comprises an input cell terminal and an output cell terminal, wherein an analog cell is configured to generate at the output cell terminal an output analog signal whose amplitude is the product of a multiplication coefficient by the amplitude of the input analog signal received at the input cell terminal, wherein all input terminals of the cells in a row are connected to a same input device terminal (x0-x4); a network of switches (00-33) for selectively interconnecting the output cell terminals of the analog cells and selectively connecting the output cell terminal of each of the analog cells to an output device terminal (p0-p7).

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First Claim