MEMORY DEVICE AND AN OPERATION METHOD THEREOF
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United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Aug 15, 2023
filing date -
Aug 15, 2023
priority date (Note) -
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Abstract
A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.
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