CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL
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United States of America
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Issued Date -
Nov 28, 2024
app pub date -
May 25, 2023
filing date -
May 25, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.
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