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Abstract

Methods for integrating copper-graphene laminate (CGL) in a multilayer PCB fabrication process and the resulting lamination stacks are disclosed. The methods include providing a core and applying a first graphene layer to the surface of the core. The methods further include applying a metal layer to the first graphene layer and applying a second graphene layer to the metal layer. Further, the methods include applying a photoresist layer to the second graphene layer and applying a protective layer to the photoresist layer. In some embodiments, the methods include applying a metallic plating to lamination stack. The methods further include drilling through the protective layer and at least one of a photoresist layer, the second graphene layer, the metal layer, the first graphene layer, and/or the core.

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First Claim