SIGNAL CONVERTER WITH DELAY ARCHITECTURE FOR CONCURRENT SIGNAL PROCESSING
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Oct 14, 2022
filing date -
Oct 14, 2022
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Abstract
Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.
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