Importance

Loading Importance Indicators...

Abstract

A system including a memory sub-system controller to transmit a data signal via a communication channel. The system includes a receiver to receive the data signal from the memory sub-system controller via an interface, the receiver comprising a decision feedback equalizer (DFE) sub-system. The DFE sub-system includes a first data detector circuit including a first tap circuit, where the first data detector circuit generates, using a first reference voltage, a first subset of detected values corresponding to the data signal. The DFE sub-system includes a second data detector circuit including a second tap circuit, where the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.

Loading the Abstract Image...

First Claim