TIMER-BASED FAULT PROTECTION CIRCUIT
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Mar 13, 2025
app pub date -
Jan 24, 2022
filing date -
Jan 24, 2022
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A timer-based fault protection circuit (100) is provided, which comprises a high voltage line (102) configured to electrically couple to a first terminal of an intrinsically safe load (ISL), a low voltage line (104) configured to electrically couple to a second terminal of the intrinsically safe load (ISL), a voltage limiter (110) and a delay/LIP enable circuit (120) electrically coupled to the high voltage line (102) and the low voltage line (104) electrically parallel to the intrinsically safe load (ISL), and a switchable low impedance path (130) electrically coupled to the high voltage line (102) and the low voltage line (104) in a shunt configuration relative to the intrinsically safe load (ISL). The voltage limiter (110) is communicatively coupled to the delay/LIP enable circuit (120) and configured to provide a signal to the delay/LIP enable circuit (120) and the delay/LIP enable circuit (120) is communicatively coupled to the switchable low impedance path (130) and configured to provide a signal to the switchable low impedance path (130).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully