METHODS FOR MAKING SEMICONDUCTOR-BASED INTEGRATED CIRCUITS
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Dec 5, 2024
filing date -
Dec 5, 2024
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Abstract
A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.
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