Importance

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Abstract

A memory includes: first to N^th register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to N^th selection signals is activated, where N is an integer equal to or greater than 2; first to N^th resource latch circuits suitable for storing first to N^th resource signals indicating availability of the first to N^th register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to N^th resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to N^th selection signals.

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First Claim