SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 9, 2024
filing date -
Sep 9, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
According to an embodiment, a clock signal is input to clock terminals of first and second FFs. A first signal from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs inversion calculation on a second signal from a Q terminal of the second FF. A signal from the first inverter is input to a D terminal of the first FF. A second inverter performs inversion calculation on the first signal. (L−1) adders each calculate a different bit of a Gray code by an addition operation based on a carry signal. A circuit block generates a carry signal for a first adder based on a logical product of the first/second signals. The circuit block generates carry signals of second to (L−1)th adders based on the second signal and a signal from the second inverter.
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