TIMING CONTROL CIRCUIT OF MEMORY DEVICE WITH TRACKING WORD LINE AND TRACKING BIT LINE
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United States of America Patent
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Issued Date -
Mar 27, 2025
app pub date -
Dec 9, 2024
filing date -
Dec 9, 2024
priority date (Note) -
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Abstract
A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
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