INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL ISOMERIC MOIETIES AND NON-THERMAL ISOMERIC MOIETIES

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250112144A1
SERIAL NO

18476561

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy monomers, and the thermal isomeric linkages including a cis-dibenzocyclooctane (DBCO) moiety or a tetra derivative DBCO moiety. In some embodiments, the dielectric material includes an epoxy having thermal isomeric epoxy monomers including a cis-DBCO moiety or a tetra derivative DBCO moiety, non-thermal isomeric epoxy monomers, and non-thermal isomeric linkages. In some embodiments, the dielectric material includes a bismaleimide resin or a polyimide resin having non-thermal isomeric monomers and thermal isomeric monomers including a cis-DBCO moiety or a tetra derivative DBCO moiety.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Saber, Mohamed R College Station, US 4 0

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