SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING OF INTEGRATED CIRCUITS

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United States of America

APP PUB NO 20250116703A1
SERIAL NO

18522725

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Abstract

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An integrated circuit (IC), including a recording circuit and a clocking system, is provided. During a capture phase of an at-speed testing of the IC, the recording circuit records a number of clock pulses of a test clock signal and generates configuration data indicative of the recorded number of the clock pulses. The clocking system receives a reference clock signal and the configuration data and generates an at-speed clock signal. During the capture phase, the at-speed clock signal includes clock pulses that are extracted from the reference clock signal based on the configuration data. A count of the extracted clock pulses is equal to the recorded number of clock pulses of the test clock signal. The at-speed testing of the IC is enabled based on the at-speed clock signal.

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Patent Owner(s)

Patent OwnerAddress
NXP B V60 HIGH TECH PARK EINDHOVEN 5656 AG EINDHOVEN NORTH BRABANT PROVINCE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gupta, Chandan Greater Noida, IN 8 9
Pandey, Saumya Raseda, IN 2 0
Thummar, Denish Surat, IN 1 0

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