PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250118705A1
SERIAL NO

18984446

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Abstract

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A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR TECH LLCNot Provided

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alatorre, Roseann San Jose, US 14 535
Chau, Ellis San Jose, US 45 2407
Co, Reynaldo Santa Cruz, US 37 1300
Damberg, Philip Cupertino, US 53 1335
Wang, Wei-Shun Palo Alto, US 29 931
Yang, Se Young Cupertino, US 20 717

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