High speed resettable dynamic counter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 1, 1980
Grant Date -
N/A
app pub date -
Sep 12, 1977
filing date -
Sep 27, 1976
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A counter stage includes a clocked transmission gate which, when turned on, couples the output of the stage back to its input. A resetting circuit is connected to the input of the stage for selectively clamping the input to a fixed voltage level representative of a logic one or a logic zero. The resetting circuit is enabled only when the clocked transmission gate is turned off, whereby no current can flow from, or to, the output via the resetting means. This enables high speed of reset since the input of the stage is then easily discharged (or charged) to the selected fixed level via the resetting circuit.
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Cited Art Landscape
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