Semiconductor memory with pulse controlled column load circuit
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United States of America Patent
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-
Jan 22, 1980
Grant Date -
N/A
app pub date -
Mar 22, 1978
filing date -
Mar 24, 1977
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device comprises a matrix array of a plurality of memory cells wherein a load circuit connected to column lines of the matrix array for charging the column lines is enabled to provide different resistance values between the actions of charging and discharging the column lines.
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