Frequency divider circuit with selectable integer/non-integer division
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United States of America Patent
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-
Mar 11, 1980
Grant Date -
N/A
app pub date -
Mar 20, 1978
filing date -
Mar 20, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A divide circuit is provided for dividing an input signal of frequency N by the quantity M+0.5, where N is any positive number and M is an integer. In one embodiment a clock signal operating at a frequency of 3.5 megahertz is divided by 3.5, yielding an output signal of 1 megahertz. Additional logic means may be provided responsive to a control signal for dividing the input signal by the quantity M+1 for a given state of the control signal.
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