Importance

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Abstract

A data transmission system which includes stations connected in a closed loop configuration with interface capabilities at each station to connect to an external data processor. Through this configuration simultaneous transmission of data among processors connected to stations on the loop can be carried out by transmission of data around the loop between particular stations. Data is transmitted from a first processor to its individual station connected to the loop. This first station formats the data received from the first processor into frames of multi-bit configuration which are transmitted around the loop to a second station which is connected to a second processor. Data received by the second station is stored and transmitted to the second processor. During the time that this transmission from the first processor to the second processor is being carried out a transmission between other processors connected to stations on the loop can also be carried out. Each station on the loop receives all frames being serially transmitted around the loop and after examination of the address section of the frame will keep frames designated for that particular station and will pass on those frames addressed to other stations on the loop. Each of the stations connected in the loop is an identical unit including a clock generator and synchronizer with no master station being designated for control functions, therefore, no control lines other than a clock timing line are included in the loop. A bypass function selects an alternate path around a station on the loop to permit faulty stations to temporarily be disconnected from the loop bus. Each station has a purging capability which permits frames which have parity errors or illegitimate addresses to be removed from the loop.

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First Claim