Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 13, 1980
Issued Date -
N/A
app pub date -
Dec 15, 1978
filing date -
Feb 24, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully