Sample and hold circuit
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United States of America Patent
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-
Jun 24, 1980
Grant Date -
N/A
app pub date -
Nov 7, 1977
filing date -
Nov 7, 1977
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A low drift sample and hold circuit is disclosed comprising a transconductance input buffer coupled at its output to a plurality of CMOS inverters through a respective plurality of CMOS switches. The appropriate switches are momentarily addressed by a micro-processor while applying a respective input value to the buffer. The buffer is de-activated prior to the opening of the switch to prevent errors between the sampled and held values.
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