Round off correction logic for modified Booth's algorithm
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United States of America Patent
Stats
-
Oct 21, 1980
Grant Date -
N/A
app pub date -
Dec 6, 1978
filing date -
Dec 6, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.
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