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Abstract

A digital-to-analog converter of a pulse width modulation type in which a single counting cycle of a clock pulse counter is divided into 2.sup.m elementary periods where m represents a selected number of less significant bits of a digital input data to be converted into analog quantity and elementary pulses in number determined in dependence on the logic values of the more significant bits are distributed among the elementary periods, while supplementary elementary pulses are produced in the elementary periods selected in dependence on the logic values of the less significant bits of the digital input data. These elementary pulses are integrated for every elementary period and the integrated output value is converted into a corresponding DC analog output signal.

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