Importance

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Abstract

A power failure detection and restart system for use with a microprocessor (microcomputer) control system includes first and second cascaded voltage comparators, the first of which responds to a drop in the supply voltage supplied to the microprocessor to produce an output pulse causing a software freeze of the microprocessor. The microprocessor operates in response to the software freeze pulse to transfer the contents of certain registers thereof to a battery protected memory for temporary storage therein. A positive feed-back circuit is used on the first voltage comparator to insure its rapid and complete change of state; and this change of state signal is applied through a time delay circuit to the second voltage comparator, which produces an output signal a predetermined time after the software freeze pulse is obtained from the first voltage comparator to reset the microprocessor to an initial circuit condition. Built in hysteresis in the system is employed; so that when the power once again rises above the level sufficient to properly operate the system, the first and second voltage comparators are turned on in the same sequence they were turned off to re-establish operation of the microprocessor which picks up its routine at the point the interruption took place.

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First Claim