Importance

Loading Importance Indicators...

Abstract

A comparator is provided to produce a coincidence pulse when the combination of respective stages of a first counter which counts a first clock pulse coincides with the combination of respective stages of a second counter which counts a lower second clock pulse. Furthermore, there is provided a flip-flop circuit which is set when the combination of the outputs of the first counter becomes a predetermined state and reset by the coincidence pulse thereby producing a pulse width modulated wave whose pulse width varies gradually with time. Each of the first and second counters comprises a shift register including a plurality of serially connected binary memory elements which sequentially shift an input data. Each shift register includes a feedback circuit which feeds back the outputs of predetermined ones of the binary memory elements to the first stage memory element through an exclusive OR gate circuit.

Loading the Abstract Image...

First Claim