Apparatus for correcting multiple errors in data words read from a memory
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United States of America Patent
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Nov 25, 1980
Issued Date -
N/A
app pub date -
Jan 15, 1979
filing date -
Jan 15, 1979
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus for a semiconductor memory in a data processing system, which performs real-time single and double error detection and correction, as well as triple error detection. The syndrome of the data word read from the memory is stored when a first error is detected. Said stored syndrome is used later for error correction when a second error is detected and in parallel it is combined logically with the actual syndrome word for deriving the syndrome corresponding to the second error, said second syndrome serving for error correction. The second syndrome can also be stored for permitting real-time triple error detection.
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