Parallel interconnect for planar arrays
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United States of America Patent
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Dec 16, 1980
Grant Date -
N/A
app pub date -
Nov 29, 1978
filing date -
Nov 29, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A large scale parallel architecture in which many parallel channels numbering 10.sup.2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stacked integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective electric signal paths with a topographical one-to-one correspondence.
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