Importance

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Abstract

A multiple processor network is described whereby a 'Sender' processor can address a 'Receiver' processor within a system of processors and select the first processor which is found to be in an idle condition, and whereby a Sender can address processors of a specially indicated type. A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to 'lower level' GMM systems may access memory in 'higher level' GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an 'available' processor in a system designated under a system name, and the network will choose the processor which is 'idle' or, if there is no idle processor available, will then choose a processor which is 'not engaged', that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message.

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First Claim