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Abstract

The digital demodulator produces an information bearing analog signal which is controlled in peak-to-peak amplitude. The signal is coupled to a soft-decision demodulator which provides a multi-bit output representative of magnitude (polarity and amplitude) of the analog signal at a rate determined by the symbol clock derived from the digital demodulator. Logic means produces a logic signal of a first or second type in response to selected multi-bit outputs of the soft-decision demodulator. A logic output of the first type is produced if either the multi-bit output represents an analog signal of one polarity and amplitude greater than a predetermined amplitude, or if the multi-bit output represents an analog signal of the other polarity and amplitude less than an equal predetermined amplitude of the other polarity. The logic output is coupled to an integrating means which produces a control signal representative of deviations of the logic signal of the first type from 50% duty cycle. The deviation from 50% duty cycle determines the amplitude of the DC offset, and the polarity of the deviation determines the polarity of the offset. The output of the detector can be used in a feedback loop to eliminate the DC offset by coupling the control signal to a summing junction, to which is also coupled the analog signal.

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First Claim