Sampling clock correction circuit
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United States of America Patent
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-
Apr 21, 1981
Grant Date -
N/A
app pub date -
Oct 19, 1978
filing date -
Oct 19, 1978
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.
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