Two switchable resistive element per cell memory array
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United States of America Patent
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Jun 9, 1981
Grant Date -
N/A
app pub date -
Oct 9, 1979
filing date -
Oct 9, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory array wherein each memory cell includes a resistive device which switches from a high to a low resistance state when a potential above its programmable threshold is applied and including a reference cell per word line having a reference switchable resistive device. Using a ramp addressing potential, the array output is disabled by an output disable circuit after a reference resistive device switches which is after the switching of an addressed low threshold resistive device cell and before the switching of an addressed high threshold resistive device cell.
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