MOS/SOS Process
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United States of America Patent
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-
Jun 16, 1981
Grant Date -
N/A
app pub date -
Apr 20, 1979
filing date -
Apr 20, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An MOS process for fabricating multi-layer integrated circuits particularly suited for SOS fabrication is disclosed. Transistors are fabricated both on the substrate level and in an overlying polysilicon layer. Processing techniques for aligning source and drain regions with a buried gate are described. In one embodiment, a photoresist layer is exposed to light directed through the sapphire substrate, thereby employing the buried gate as a masking member. Laser annealing may be used to provide larger crystals of silicon in the polysilicon layer.
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