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Abstract

An improved organization for a FFT analyzer (or periodic function analyzer) having a reduced computing complexity. A modified organization comprises a simplified butterfly arithmetic unit in which the usual two coefficient registers or memories are required. By utilizing the registers as sources of a respective sum of and difference between sets of phase-shifted cosine values, the mechanization of the complex multiplier for such arithmetic butterfly unit in microcircuit or 'chip' form may be further simplified to two controllable accumlators controlled by an exclusive-NOR gate logic system responsive to the states of the complex sampled inputs of a sampled signal epoch of interest. In this way, a more efficient and higher speed device is provided for the multiplication of complex variables.

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First Claim