Common bus communication system in which the width of the address field is greater than the number of lines on the bus
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United States of America Patent
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Aug 25, 1981
Grant Date -
N/A
app pub date -
Jun 18, 1979
filing date -
Jun 18, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.
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