Execution unit for data processor using segmented bus structure
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United States of America Patent
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Oct 20, 1981
Grant Date -
N/A
app pub date -
Nov 17, 1978
filing date -
Nov 17, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.
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