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Abstract

A square root processing apparatus wherein an unknown number is sequentially squared and compared to a number whose square root is to be determined. The result of each comparison determines the state of a bit in the square root being determined. More specifically, the square root processor includes a Y register containing a number whose square root is to be determined, and an X register which is used to develop the square root of the contents of the Y register. The apparatus provides a means for initially setting the most significant bit stage of the X register to one, the remaining bit stages containing zeros. The contents of the X register are then squared by a high speed digital multiplier and compared with the contents of the Y register. If the squared number is greater than the contents of the Y register, the most significant bit stage of the X register is reset to zero. The apparatus then sets the next most significant bit stage of the X register to one and repeats the above-described sequence. The apparatus provides a means for repeating this process until all bit stages in the X register have been tested and determined, the contents of the X register then defining the square root of the number contained in the Y register.

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First Claim