Data processing system having data multiplex control apparatus
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United States of America Patent
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-
Nov 10, 1981
Grant Date -
N/A
app pub date -
Jan 31, 1979
filing date -
Jan 31, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.
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