Importance

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Abstract

A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed. By altering the set of switches, the group of memory present circuits can be conditioned to generate an output signal for indicating that the same increment is present for accessing within any one of a number of different segments thereby enabling the same board to be used in any available address slot position.

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First Claim