Importance

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Abstract

A synchronous demultiplexer at a receiving station of a TDM/PCM telecommunication system, operating on an incoming bit stream organized in frames of 32 time slots of eight bits each, comprises a random-access memory having 32 cells loaded with consecutive octets in successive time slots under the control of a writing-address generator, stepped by clock pulses extracted from the bit stream, and unloaded at a similar but not exactly identical rate under the control of a reading-address generator, stepped by locally generated clock pulses. Two series of loading pulses a and b, each lasting for a bit period t, are derived from the extracted clock pulses near the beginning and near the end, respectively, of a time slot of duration T'=8t and are fed to a control unit together with a series of unloading pulses c of length 2t occurring once per cycle T'.apprxeq.T' measured by the local clock. The control unit normally selects loading pulses a for timing the transmission of writing addresses to the random-access memory, except when these loading pulses coincide with unloading pulses c which time the transmission of reading addresses to that memory; in the latter instance, loading pulses b are substituted for pulses a.

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