Memory refresh means including means for providing refresh addresses during power failures

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4316248
SERIAL NO

06091318

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Memory control circuitry is disclosed for providing memory refresh during battery back-up operation. Memory addressing circuitry is connected between circuitry, such as a processor, providing memory refresh addresses, and memory addressing inputs. During normal main power supply operation, refresh addresses are provided to the memory from the processor. Upon occurrence of a main power supply failure, and start of battery back-up operation, the last refresh address provided by the processor is stored in the memory addressing circuitry and successively incremented to provide refresh addresses to the memory .

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Patent Owner(s)

Patent OwnerAddressTotal Patents
DATA GENERAL CORPORATIONWESTBORO, MA52

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Retter, Charles T Framingham, MA 4 212

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Patent Info (Count) # Cites Year
 
MAXIM INTEGRATED PRODUCTS, INC. (1)
* 5914543 Systems and methods for memory control 9 1995
 
POLARIS INNOVATIONS LIMITED (1)
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HITACHI MAXELL, LTD. (2)
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* 5550781 Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing 68 1995
 
VISTEON GLOBAL TECHNOLOGIES, INC. (1)
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GLOBALFOUNDRIES INC. (1)
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ROHM CO., LTD. (1)
* 5537599 CPU controlled apparatus formed on an IC 3 1994
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
* 6731563 Data backup device and step-up/step-down power supply 2 2002
 
LENOVO (SINGAPORE) PTE LTD. (1)
* 5615328 PCMCIA SRAM card function using DRAM technology 17 1995
 
HITACHI, LTD. (1)
* 4652940 Method of identifying magnetic tape as tape for journal 25 1983
 
INTERNATIONAL COMPUTERS LIMITED (1)
* 4901283 Dynamic random-access memory system with power-up and power-down refresh circuits 52 1988
 
CANON KABUSHIKI KAISHA (1)
* 4541044 Loop transmission with back-up power supply for the interface 3 1984
* Cited By Examiner