Frame resynchronization circuit for digital receiver
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United States of America Patent
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Feb 16, 1982
Grant Date -
N/A
app pub date -
Sep 11, 1980
filing date -
Sep 11, 1980
priority date (Note) -
Expired
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Abstract
Framing of a digital receiver to synchronize with a true framing pattern is realized by employing an autonomous clock to generate framing pattern bits and other timing signal, and by employing a cyclical-redundancy-check (CRC) to eliminate the possibility of framing on false framing patterns. To this end, a frame synchronization circuit detects all possible framing candidate bit positions in a received time division signal and generates a frame resynchronization pulse corresponding to the framing candidate bit positions thereby causing the autonomous clock to synchronize to the associated framing pattern. If the framing pattern on which the clock is synchronized is a false one a loss of CRC signal is generated which initiates synchronizing on the next detected framing pattern. This process is iterated until no loss of CRC signal is generated thereby indicating synchronization on the true framing pattern.
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Patent Owner(s)
- BELL TELEPHONE LABORATORIES, INCORPORATED
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Howson, Robert D | Middletown, NJ | 4 | 462 |
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