Importance

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Abstract

A phase detector generates an error signal by comparing an input data rate F:in with an output clock rate F:out. The error signal is amplified and applied to the base of an emitter follower circuit. Current from a discharging capacitor within a clock ramp generator flows through the emitter follower and the emitter impedance. The ramp current is controlled by the error signal. The ramp rate F:out is determined by the peak to peak ramp voltage and by the rate of discharge of the ramp capacitor. Variations in the error signal due to F:in drift, cause a compensating change in F:out for continuously maintaining sync between F:in and F:out within each passband. Multi-passband capability is provided by a multi-level current generator which also supplies current through the emitter impedance. The ramp current is reduced to a lower level by an amount equal to the current from the multi-level current source due to the emitter follower action. The ramp period is prolonged by the lower discharge ramp current placing the operation of the synchronizer in a lower passband. Each current level from the multi-level source establishes a separate passband of operation.

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First Claim