Method of and system for routing in a packet-switched communication network
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 16, 1982
Issued Date -
N/A
app pub date -
Feb 8, 1980
filing date -
Apr 10, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully