Importance

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Abstract

A receiving station of a data-transmission system decodes an incoming pulse train in the shape of a differentially biphase-coded carrier wave whose cycles represent rspective message bits; the wave undergoes a phase reversal at the beginning of every cycle in which the transmitted binary signal has the logical value '1' but does not change in phase when that value is '0'. The received pulse train is differentiated to yield either one or two spikes during each cycle, one such spike invariably occurring in the middle of a cycle. Since only these periodically recurring spikes determine the instants at which the carrier wave must be sampled during decoding, a gate in the differentiator output is blocked during part of each cycle by a locally generated square wave which also controls the sampling. A phase detector comprises a flip-flop, settable by the complement of the local square wave and resettable by the unsuppressed spikes, whose set output works into an AND gate also receiving the local square wave and a quadrature replica thereof overlapping same for a quarter-cycle whereby that gate conducts if the period of overlap coincides with the setting of the flip-flop, i.e. when blocking takes place at the wrong time. Resulting coincidence pulses are integrated and, when recurring sufficiently often and fast, give rise to an error pulse shifting the local square wave by half a cycle.

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First Claim