Semiconductor read/write memory array having serial access
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United States of America Patent
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-
May 18, 1982
Grant Date -
N/A
app pub date -
Nov 23, 1979
filing date -
Nov 23, 1979
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.
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