Binary word processing method using a high-speed sequential adder
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United States of America Patent
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-
Jun 22, 1982
Grant Date -
N/A
app pub date -
Apr 10, 1980
filing date -
Apr 12, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The words to be added together by the high-speed sequential adder are stored in shift registers 1.sub.l to 1.sub.p whose serial outputs are connected to the corresponding inputs of a transcoder 2 producing the binary number of '1's' for each bit weight of the words to be added. This value is sent to an adder-divider 4 which adds it to the number of carried '1's' from the immediately lesser weight and divides this sum by 2, sending the fractional part of this half-sum to an output register 5 and the whole-number part to a carry register. Application: digital filters for PCM telephone switching.
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