Importance

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Abstract

A bipolar memory circuit is provided with a delay circuit which receives a write enabling signal, a gate circuit which detects the coincidence between an input signal and an output signal of the delay circuit, and a circuit which is started by an output signal of the gate circuit and which provides a pulse signal of a fixed time. The operation of a write driver circuit in the bipolar memory circuit is controlled by the pulse signal. Noise interfering in the write enabling signal are neglected by the use of the delay circuit and the gate circuit. The pulse width of the write enabling signal is permitted to be made smaller than the pulse width of the pulse signal required by the write driver circuit.

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First Claim