Method for forming electrical connecting lines by monitoring the etch rate during wet etching

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United States of America Patent

PATENT NO 4338157
SERIAL NO

06185439

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Abstract

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A method for forming a electrical interconnections, according to the invention, comprises forming number of semiconductor circuit elements on one semiconductor substrate, depositing an electrically conductive layer on substantially the entire surface of the semiconductor substrate, etching the electrically conductive layer patterned by the photolithography, for example, coating a photoresist on the electrically conductive layer, placing a mask of a pattern of electrical connecting lines on the photoresist-coated conductive layer and exposing the assembly to actinic rays to effect a development treatment, then placing one electrode composed of the electrochemically same material as that of the electrically conductive layer so that at least one point of said one electrode is brought into contact with the electrically conductive layer, dipping the assembly in an etching solution while using as the other electrode an electric conductor composed of a material electrochemically different from the material of the electrically conductive layer, performing wet chemical etching of the electrically conductive layer while measuring an electric current flowing between the two electrodes, and terminating etching of the electrically conductive layer when said current largely decreases or continuing etching for a certain time after said current largely decreases and is reduced below a timely determined level whereby electrical interconnections are formed for the respective semiconductor circuit elements on the semiconductor substrate.

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Patent Owner(s)

Patent OwnerAddress
SIGMA CORPORATION2-8-15 KURIGI ASAO-KU KAWASAKI-SHI KANAGAWA 215-0033

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kanda, Kunihiko Yokohama, JP 2 74

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