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Abstract

A fully duplicated memory system for a single central processing unit (CPU) is disclosed. The memory system comprises a primary and a secondary control unit and a primary memory bank and a secondary memory bank. Each memory bank comprises one memory controller and a plurality of memory modules (e.g. six memory modules). Each memory module stores a plurality of binary words in distinct addressable storage locations with a unique address code defining both one distinct addressable storage location in a memory module in the first memory bank and one distinct addressable storage location in a memory module in the second memory bank. A random access memory (RAM) stores an indication of the read and write status of each memory module in both the first and second memory banks. One of the control units, responsive to both the CPU and the RAM determines which memory bank (primary or secondary) is accessed in response to a read or a write command from the CPU addressed to the memory banks.

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First Claim